Continuous Input/Output Procedure

The setting procedures for sampling (input) and generating (output) using the bus master transfer functions are described here.

Setting Sampling/Generating Conditions

Set the sampling/generating conditions once the initialization and mode settings are complete.
There are three types of sampling/generating conditions, namely the start condition setting (DioDmSetStartTrg) which sets conditions for starting the input/output (software start, external start, etc.), the clock condition setting (DioDmSetClockTrg) which sets input/output timing (internal clock, external clock, etc.), and the stop condition setting (DioDmSetStopTrg) which sets conditions for completing the input/output (software stop, suspension of specified number, etc.).

Also, there are condition setting functions that supplement each setting (i.e. number settings in the case of suspension of number specification).

Once those sampling/generating conditions are set after initialization, subsequent operations are carried out under the same conditions provided that the data is input/output in the same way. If data is transferred under different operating conditions per transfer, settings that need to be modified should be reset prior to the start of the transfer.

Sampling/generating patterns can be selected from the following table.

	Start conditions	Clock conditions	Stop conditions
Type Symbol	Software start DIODM_START_SOFT	Internal clock DIODM_CLK_CLOCK	Software stop DIODM_STOP_SOFT
Type Symbol	External start rising DIODM_START_EXT_RISE	External clock DIODM_CLK_EXT_TRG	External stop rising DIODM_STOP_EXT_RISE
Type Symbol	External start falling DIODM_START_EXT_FALL	Handshake DIODM_CLK_HANDSHAKE	External stop falling DIODM_STOP_EXT_FALL
Type Symbol	Pattern matching(input only) DIODM_START_PATTERN	SC connector EXTSIG1 DIODM_CLK_EXTSIG_1	SC connector EXTSIG1 DIODM_STOP_EXTSIG_1
Type Symbol	SC connector EXTSIG1 DIODM_START_EXTSIG_1	SC connector EXTSIG2 DIODM_CLK_EXTSIG_2	SC connector EXTSIG2 DIODM_STOP_EXTSIG_2
Type Symbol	SC connector EXTSIG2 DIODM_START_EXTSIG_2	SC connector EXTSIG3 DIODM_CLK_EXTSIG_3	SC connector EXTSIG3 DIODM_STOP_EXTSIG_3
Type Symbol	SC connector EXTSIG3 DIODM_START_EXTSIG_3

Reset

Counter values of the previous transfer and FIFO contents must be reset in accordance with the reset functions (DioDmReset).

Buffer setting (Sampling: input)

With regard to bus master transfer, set the memory address of the transfer destination on the board and when transfer is started the data is transferred from the board to the memory address.
Thus, a buffer area where input values are to be received must be set on the board before the start of any transfer (DioDmSetBuff).

The buffer area that has been set is locked to prevent physical movement to other addresses. The locked area is unlocked upon completion of the transfer. Transferal to an unlocked area is risky, so a buffer must be set for each transfer.

If a heap-and-stack buffer area is acquired, that area must not be released until the transfer is complete. If the buffer area is released before completion of the transfer, that area will be used for other processes.
If data is transferred to the area used for other processing, exceptions may be generated with the program.
It is recommended that the area to be used for the BusMaster transfer be changed to a global area if program safety is deemed important.

Single transfers that complete transferal when all data is transferred into the buffer and unlimited transfers that repeatedly transfer data indefinitely to the same buffer area are prepared for transfer operations.

Buffer setting (Generating: output)

The originator's memory address should be set in the hardware for bus master transfer, and data should be transferred from that memory address to the FIFO within the board before executing generation.
The buffer area in which output data is stored must be set in the hardware to execute output (DioDmSetBuff).

The set buffer area is locked to prevent physical movement to another address. The locked area is unlocked on completion of transfer. A buffer must be set for each transfer.

If a heap-and-stack buffer area is acquired, that area must not be released until the transfer is complete. If the buffer area is released before completion of the transfer, that area will be used for other processes, and data other than that to be output is written. If transfer is executed under that status, erroneous data may be output.
It is recommended that the area to be used for the BusMaster transfer be changed to a global area if program safety is deemed important.

Single transfers that complete transferal when all data is transferred into the buffer and unlimited transfers that repeatedly transfer data indefinitely to the same buffer area are prepared for transfer operations.
When the same data needs to be repeated for a specific number of times, a size sufficient for that number of times should be prepared and a single transfer used.

Start

Operation is started after setting the sampling/generating conditions, and buffers (DioDmStart).
Sampling/generating is started when the start conditions are satisfied while it is operating, and sampling/generating ends when the stop conditions are satisfied. In the case where software start is set, sampling/generating is started when the DioDmStart functions are called.

Input data is first stored into FIFO within the board and then transferred to the applied memory when the bus is available.

Output data is immediately sent to FIFO within the board and output externally when the clock conditions are met.

Stop/Transfer completion

Sampling/generating ends when the stop conditions are satisfied.
There are two ways to catch the end of the operation from the application - one being the status monitoring method (DioDmGetStatus) and the other is to confirm the ending with a message (DioDmSetStopEvent). Processing is also possible by confirming the number of transfers during operation (DioDmGetCount). The locked buffer area is unlocked once sampling/generating has finished.