AioSetEcuSignal

Function

Sets the signal of event controller.

Format

Ret = AioSetEcuSignal ( Id , Destination , Source )

Parameters

Id [ C, C++ : short ] [ Python : ctypes.c_short ]
Specifies the ID retrieved from AioInit.

Destination [ C, C++ : short ] [ Python : ctypes.c_short ]
Specifies the destination signal from the following range.

Destination signal

Marco

Value (Decimal number)

Analog input sampling clock period

AIOECU_DEST_AI_CLK

4

Analog input conversion start signal

AIOECU_DEST_AI_START

0

Analog input conversion stop signal

AIOECU_DEST_AI_STOP

2

Analog output generating clock period

AIOECU_DEST_AO_CLK

36

Analog output conversion start signal

AIOECU_DEST_AO_START

32

Analog output conversion stop signal

AIOECU_DEST_AO_STOP

34

Counter0 UP clock signal

AIOECU_DEST_CNT0_UPCLK

134

Counter1 UP clock signal

AIOECU_DEST_CNT1_UPCLK

135

Counter0, Timer0 operation start signal

AIOECU_DEST_CNT0_START

128

Counter1, Timer1 operation start signal

AIOECU_DEST_CNT1_START

129

Counter0, Timer0 operation stop signal

AIOECU_DEST_CNT0_STOP

130

Counter1, Timer1 operation stop signal

AIOECU_DEST_CNT1_STOP

131

Synchronous bus bus master signal1

AIOECU_DEST_MASTER1

104

Synchronous bus bus master signal2

AIOECU_DEST_MASTER2

105

Synchronous bus bus master signal3

AIOECU_DEST_MASTER3

106

Source [ C, C++ : short ] [ Python : ctypes.c_short ]
Specifies the source signal from the following values.

Source signal

Macro

Value (Decimal number)

Analog input internal clock signal

AIOECU_SRC_AI_CLK

4

Analog input external clock signal

AIOECU_SRC_AI_EXTCLK

146

Analog input external trigger start signal

AIOECU_SRC_AI_TRGSTART

144

Analog input level trigger start signal

AIOECU_SRC_AI_LVSTART

28

Analog input conversion times stop signal (Not delay)

AIOECU_SRC_AI_STOP

17

Analog input conversion times stop signal (Delay)

AIOECU_SRC_AI_STOP_DELAY

18

Analog input level trigger stop signal

AIOECU_SRC_AI_LVSTOP

29

Analog input external trigger stop signal

AIOECU_SRC_AI_TRGSTOP

145

Analog output internal clock signal

AIOECU_SRC_AO_CLK

66

Analog output external clock signal

AIOECU_SRC_AO_EXTCLK

149

Analog output external trigger start signal

AIOECU_SRC_AO_TRGSTART

147

Analog output specified times output stop signal (FIFO)

AIOECU_SRC_AO_STOP_FIFO

352

Analog output specified times output stop signal (RING)

AIOECU_SRC_AO_STOP_RING

80

Analog output external trigger stop signal

AIOECU_SRC_AO_TRGSTOP

148

Counter0 UP clock signal

AIOECU_SRC_CNT0_UPCLK

150

Counter1 UP clock signal

AIOECU_SRC_CNT1_UPCLK

152

Counter0 comparison count match

AIOECU_SRC_CNT0_CMP

288

Counter1 comparison count match

AIOECU_SRC_CNT1_CMP

289

Synchronous bus bus slave signal1

AIOECU_SRC_SLAVE1

136

Synchronous bus bus slave signal2

AIOECU_SRC_SLAVE2

137

Synchronous bus bus slave signal3

AIOECU_SRC_SLAVE3

138

Ai, Ao, Cnt, Tm software start signal

AIOECU_SRC_START

384

Ai, Ao, Cnt, Tm software stop signal

AIOECU_SRC_STOP

385

Return values

Ret [ C, C++ : long ] [ Python : ctypes.c_long ]

Return values

Content

0

Normality completion

7

Execute AioResetDevice function because the device has recovered from standby mode

10001

Invalid Id was specified
Use the Id retrieved from AioInit to specify the Id in this function.

10002

AIO driver can't be called
At first, perform AioInit function.

17000

The value of Destination is outside the designated range of the function

17001

The value of Source is outside the designated range of the function

20001

This function can't be used by this device

20002

Can not use while by another device works
To use this function, analog input and output, counter, timer operation must be stopped.

20003

Can not use because another process is using the device
When another process is using the device, all functions except for those that support multi-process can not be performed.

27000

The value of Destination is outside the designated range of the device being used

27001

The value of Source is outside the designated range of the device being used

27002

An invalid connection

Initial values

Destination signal

Source signal

Analog input sampling clock period

Analog input internal clock signal

Analog input conversion start signal

Not connect

Analog input conversion stop signal

Analog input conversion times stop signal (No delay)

Analog output generating clock period

Analog output internal clock signal

Analog output conversion start signal

Not connect

Analog output conversion stop signal

Analog output specified times output stop signal (FIFO)

Counter0 UP clock signal

Counter0 UP clock signal

Counter1 UP clock signal

Counter1 UP clock signal

Counter0, Timer0 operation start signal

Not connect

Counter1, Timer1 operation start signal

Not connect

Counter0, Timer0 operation stop signal

Not connect

Counter1, Timer1 operation stop signal

Not connect

Synchronous bus bus master signal1

Not connect

Synchronous bus bus master signal2

Not connect

Synchronous bus bus master signal3

Not connect

Remarks

Multifunctional operation can be performed by switching the control signal among Ai, Ao, Cnt.
The control relative to Synchronous bus bus is set by using this function too.

If the device is in operation, the function cannot be performed.

Some combinations can be used while some combinations cannot be used.

 

Specifications based on devices

[AIO-123202G-PE, AIO-123202UG-PE, AIO-163202G-PE, AIO-163202UG-PE]
[AIO-163202F-PE, ADA16-32/2(PCI)F]

 

Source / Destination

Analog input sampling clock period

Analog input conversion start signal

Analog input conversion stop signal

Analog output generating clock period

Analog output conversion start signal

Analog output conversion stop signal

Counter0 UP clock signal

Counter1 UP clock signal

Counter0, Timer0 operation start signal

Counter1, Timer1 operation start signal

Counter0, Timer0 operation stop signal

Counter1, Timer1 operation stop signal

Synchronous bus bus master signal1

Synchronous bus bus master signal2

Synchronous bus bus master signal3

Analog input
internal clock signal

-

 

 

Yes

 

 

 

 

 

 

 

 

Yes

Yes

Yes

Analog input
external clock signal

-

 

 

Yes

 

 

 

 

 

 

 

 

 

 

 

Analog input
external trigger start signal

 

-

 

 

Yes

Yes

 

 

No

No

No

No

 

 

 

Analog input
level trigger start signal

 

-

 

 

Yes

Yes

 

 

No

No

No

No

Yes

Yes

Yes

Analog input
conversion times stop signal (Not delay)

 

 

-

 

Yes

Yes

 

 

No

No

No

No

Yes

Yes

Yes

Analog input
conversion times stop signal (Delay)

 

 

-

 

Yes

Yes

 

 

No

No

No

No

Yes

Yes

Yes

Analog input
level trigger stop signal

 

 

-

 

Yes

Yes

 

 

No

No

No

No

Yes

Yes

Yes

Analog input
external trigger stop signal

 

 

-

 

Yes

Yes

 

 

No

No

No

No

 

 

 

Analog output
internal clock signal

Yes

 

 

-

 

 

 

 

 

 

 

 

Yes

Yes

Yes

Analog output
external clock signal

Yes

 

 

-

 

 

 

 

 

 

 

 

 

 

 

Analog output
external trigger start signal

 

Yes

Yes

 

-

 

 

 

No

No

No

No

 

 

 

Analog output specified times
output stop signal (FIFO)

 

Yes

Yes

 

 

-

 

 

No

No

No

No

Yes

Yes

Yes

Analog output specified times
output stop signal (RING)

 

Yes

Yes

 

 

-

 

 

No

No

No

No

Yes

Yes

Yes

Analog output
external trigger stop signal

 

Yes

Yes

 

 

-

 

 

No

No

No

No

 

 

 

Counter0
UP clock signal

 

 

 

 

 

 

-

 

 

 

 

 

Yes

Yes

Yes

Counter1
UP clock signal

 

 

 

 

 

 

 

-

 

 

 

 

Yes

Yes

Yes

Counter0
comparison count match

 

Yes

Yes

 

Yes

Yes

 

 

 

 

 

 

Yes

Yes

Yes

Counter1
comparison count match

 

Yes

Yes

 

Yes

Yes

 

 

 

 

 

 

Yes

Yes

Yes

Synchronous bus
slave signal1

Yes

Yes

Yes

Yes

Yes

Yes

 

 

 

 

 

 

 

 

 

Synchronous bus
slave signal2

Yes

Yes

Yes

Yes

Yes

Yes

 

 

 

 

 

 

 

 

 

Synchronous bus
slave signal3

Yes

Yes

Yes

Yes

Yes

Yes

 

 

 

 

 

 

 

 

 

Ai, Ao, Cnt, Tm
software start signal

 

-

-

 

-

-

 

 

No

No

No

No

Yes

Yes

Yes

Ai, Ao, Cnt, Tm
software stop signal

 

-

-

 

-

-

 

 

No

No

No

No

Yes

Yes

Yes

Yes: The connectible combinations (Connectible)
No: The combinations unsupported now (Not connectible)
-: When the conversion start condition etc. is selected other than Event Controller Output, driver will select the optimal combination and make a connection automatically (Not connectible by using API)
Others: The combinations that cannot be connected (Not connectible)

 

[AI-1664UG-PE]
Since AI-1664UG-PE has no corresponding function on hardware, [Analog output] and [Counter1] can not be set.

 

Source / Destination

Analog input sampling clock period

Analog input conversion start signal

Analog input conversion stop signal

Counter0 UP clock signal

Counter0, Timer0 operation start signal

Counter0, Timer0 operation stop signal

Synchronous bus bus master signal1

Synchronous bus bus master signal2

Synchronous bus bus master signal3

Analog input
internal clock signal

-

 

 

 

 

 

Yes

Yes

Yes

Analog input
external clock signal

-

 

 

 

 

 

 

 

 

Analog input
external trigger start signal

 

-

 

 

No

No

 

 

 

Analog input
level trigger start signal

 

-

 

 

No

No

Yes

Yes

Yes

Analog input
conversion times stop signal (Not delay)

 

 

-

 

No

No

Yes

Yes

Yes

Analog input
conversion times stop signal (Delay)

 

 

-

 

No

No

Yes

Yes

Yes

Analog input
level trigger stop signal

 

 

-

 

No

No

Yes

Yes

Yes

Analog input
external trigger stop signal

 

 

-

 

No

No

 

 

 

Counter0
UP clock signal

 

 

 

-

 

 

Yes

Yes

Yes

Counter0
comparison count match

 

Yes

Yes

 

 

 

Yes

Yes

Yes

Synchronous bus
slave signal1

Yes

Yes

Yes

 

 

 

 

 

 

Synchronous bus
slave signal2

Yes

Yes

Yes

 

 

 

 

 

 

Synchronous bus
slave signal3

Yes

Yes

Yes

 

 

 

 

 

 

Ai, Ao, Cnt, Tm
software start signal

 

-

-

 

No

No

Yes

Yes

Yes

Ai, Ao, Cnt, Tm
software stop signal

 

-

-

 

No

No

Yes

Yes

Yes

Yes: The connectible combinations (Connectible)
No: The combinations unsupported now (Not connectible)
-: When the conversion start condition etc. is selected other than Event Controller Output, driver will select the optimal combination and make a connection automatically (Not connectible by using API)
Others: The combinations that cannot be connected (Not connectible)

 

[AIO-163202FX-USB]
Since AIO-163202FX-USB has no corresponding function on hardware, [Synchronous bus bus slave signal] and [Synchronous bus bus master signal] can not be set.

 

Source / Destination

Analog input sampling clock period

Analog input conversion start signal

Analog input conversion stop signal

Analog output generating clock period

Analog output conversion start signal

Analog output conversion stop signal

Counter0 UP clock signal

Counter1 UP clock signal

Counter0, Timer0 operation start signal

Counter1, Timer1 operation start signal

Counter0, Timer0 operation stop signal

Counter1, Timer1 operation stop signal

Analog input
internal clock signal

-

 

 

Yes

 

 

 

 

 

 

 

 

Analog input
external clock signal

-

 

 

Yes

 

 

 

 

 

 

 

 

Analog input
external trigger start signal

 

-

 

 

Yes

Yes

 

 

No

No

No

No

Analog input
level trigger start signal

 

-

 

 

Yes

Yes

 

 

No

No

No

No

Analog input
conversion times stop signal (Not delay)

 

 

-

 

Yes

Yes

 

 

No

No

No

No

Analog input
conversion times stop signal (Delay)

 

 

-

 

Yes

Yes

 

 

No

No

No

No

Analog input
level trigger stop signal

 

 

-

 

Yes

Yes

 

 

No

No

No

No

Analog input
external trigger stop signal

 

 

-

 

Yes

Yes

 

 

No

No

No

No

Analog output
internal clock signal

Yes

 

 

-

 

 

 

 

 

 

 

 

Analog output
external clock signal

Yes

 

 

-

 

 

 

 

 

 

 

 

Analog output
external trigger start signal

 

Yes

Yes

 

-

 

 

 

No

No

No

No

Analog output specified times
output stop signal (FIFO)

 

Yes

Yes

 

 

-

 

 

No

No

No

No

Analog output specified times
output stop signal (RING)

 

Yes

Yes

 

 

-

 

 

No

No

No

No

Analog output
external trigger stop signal

 

Yes

Yes

 

 

-

 

 

No

No

No

No

Counter0
UP clock signal

 

 

 

 

 

 

-

 

 

 

 

 

Counter1
UP clock signal

 

 

 

 

 

 

 

-

 

 

 

 

Counter0
comparison count match

 

Yes

Yes

 

Yes

Yes

 

 

 

 

 

 

Counter1
comparison count match

 

Yes

Yes

 

Yes

Yes

 

 

 

 

 

 

Ai, Ao, Cnt, Tm
software start signal

 

-

-

 

-

-

 

 

No

No

No

No

Ai, Ao, Cnt, Tm
software stop signal

 

-

-

 

-

-

 

 

No

No

No

No

Yes: The connectible combinations (Connectible)
No: The combinations unsupported now (Not connectible)
-: When the conversion start condition etc. is selected other than Event Controller Output, driver will select the optimal combination and make a connection automatically (Not connectible by using API)
Others: The combinations that cannot be connected (Not connectible)

 

[AI-1204Z-PE]
Since AI-1204Z-PE has no corresponding function on hardware, [Analog output] and [Counter] can not be set.

 

Source / Destination

Analog input sampling clock period

Analog input conversion start signal

Analog input conversion stop signal

Synchronous bus bus master signal1

Synchronous bus bus master signal2

Synchronous bus bus master signal3

Analog input
internal clock signal

-

 

 

Yes

Yes

Yes

Analog input
external clock signal

-

 

 

 

 

 

Analog input
external trigger start signal

 

-

 

 

 

 

Analog input
level trigger start signal

 

-

 

Yes

Yes

Yes

Analog input
conversion times stop signal (Not delay)

 

 

-

Yes

Yes

Yes

Analog input
level trigger stop signal

 

 

-

Yes

Yes

Yes

Analog input
external trigger stop signal

 

 

-

 

 

 

Synchronous bus
slave signal1

Yes

Yes

Yes

 

 

 

Synchronous bus
slave signal2

Yes

Yes

Yes

 

 

 

Synchronous bus
slave signal3

Yes

Yes

Yes

 

 

 

Ai, Ao, Cnt, Tm
software start signal

 

 

 

Yes

Yes

Yes

Ai, Ao, Cnt, Tm
software stop signal

 

 

 

Yes

Yes

Yes

Yes: The connectible combinations (Connectible)
-: When the conversion start condition etc. is selected other than Event Controller Output, driver will select the optimal combination and make a connection automatically (Not connectible by using API)
Others: The combinations that cannot be connected (Not connectible) 

 

Example

The analog input internal clock signal is connected with the analog output generating clock period.

C, C++

long Ret;
Ret = AioSetEcuSignal ( Id , AIOECU_DEST_AO_CLK  , AIOECU_SRC_AI_CLK );
 

Python

Ret = ctypes.c_long()
Ret.value = caio.AioSetEcuSignal ( Id , caio.AIOECU_DEST_AO_CLK , caio.AIOECU_SRC_AI_CLK )